Network switches/switching units are at the core of any communication network. A network switch typically includes an on-chip crossbar having a plurality of (N) input ports configured to fetch and receive packet data from a plurality of memory banks, and a plurality of (N) output port groups/network interfaces configured to output the data from the memory banks to other network devices. During its operation, the on-chip crossbar of the network switch routes the packet data received at the input ports to the port groups through multiple processing stages according to control logic of the network switch. The hardware cost of a N×N on-chip full crossbar of data/word width w is O(w N N).
Benes network is a rearrangeable nonblocking network, which can realize any arbitrary permutation between N input ports and N port groups of the on-chip crossbar via 2 log2N−1 stages, each containing N/2 2×2 crossbar switching nodes/units as discussed in details below. Routing of the packet data through the Benes network can be controlled and re-arranged via external control signals to the switching units within the stages of the Benes network. Given the demand for high-speed, high-data throughput of the network switch, it is desirable to implement routing control for the on-chip crossbar of the network switch based on the Benes network for high-speed parallel packet routing implementation with support of partial permutations between the input ports and the port groups of the on-chip crossbar.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent upon a reading of the specification and a study of the drawings.